1. Field of the Invention
The invention relates generally to computer memory device controllers, and more specifically, to a device and method for tracking the bank state of a memory device.
2. Description of Related Art
Computer main memory typically comprises a group of memory devices, such as dynamic random access memory (DRAM) devices, which include several banks of data storage cells arranged in arrays of rows and columns. A memory controller works in conjunction with the memory devices to read and write data to the memory device and perform other memory device control tasks, such as memory refresh. To access the memory locations, the memory controller provides an address signal that identifies a specific memory device, a bank within the device, and a row and column address within the bank.
FIG. 1 illustrates a simplified block diagram of a prior art memory device 10, which includes four memory banks 12. Each memory bank 12 includes data storage cells arranged in rows and columns (not shown). A row address buffer 14 holds a row address portion of a memory address received via address input terminals 16. A row decoder 18 decodes an output of the row address buffer 14 to select a row of data from the identified memory bank 12. A bank of sense amplifiers 20 stores and amplifies data from the row selected from the memory bank 12 by the row decoder 18, as row data for one page. A column address buffer 22 stores a column address received through the address input terminals 16, and transfers the column address to a column decoder 24, which selects data corresponding to the designated column from page data stored in the sense amplifiers 20 associated with the designated memory bank 12. A data input/output circuit 26 reads the selected data from the sense amplifiers 20 associated with the selected memory bank 12, or provides data to the sense amplifiers 20 to be written to the selected memory bank 12.
When data are held in the sense amplifiers 20 associated with the selected memory bank 12, the bank 12 is considered "open." When no data are held in the sense amplifiers 20, the bank 12 is considered "closed." When the data read or write is complete, the memory bank 12 may be closed, until it is selected for another read or write. Conventional memory devices, such as that illustrated in FIG. 1, have a bank of sense amplifiers 20 for each memory bank 12 in the memory device 10. This is considered an "independent" bank structure, since individual memory banks may be operated independent of the other memory banks within the memory device.